Front End ASIC RTL/Logic Senior Design Engineer

Job Details: Job Description: Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi Giga. Hz design. Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.

Work on post Silicon debug/characterization support of the designs.

Qualifications

BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience Strong in communication, leadership, investigation, problem solving & analytical skill Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT.

Knowledge scripting desirable Job Type: Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.