Senior Manufacturing and System Co-Design Workflow Engineer

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs.

When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem.

What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10+, before silicon exposes the discrepancy.

The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage.

Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready harness: CLIs, MCPs, bug and spec retrieval, human-in-the-loop checkpoints, and evaluation-based CI gates running against real silicon workflows. This is the infrastructure that makes AI genuinely usable in a rigorous engineering environment.

Cross-Org Adoption Across Design, Operations & DFX: Drive adoption of SMAC methodology and tooling across Post Silicon (Prod), Operations, and DFX (DFT/DFP) teams. The infrastructure only works if it's actually used, and the best candidates in this role have a track record of getting resistant partners across the line.

What we need to see: A BS, MS, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or Systems Engineering, with 8+ years in system software, silicon bring-up, or productization engineering. Strong Python and systems skills are essential; we want to see production services and data pipelines shipped.

Extra credit if subject matter experts are today depending on an LLM-backed tool you built. Deep understanding of the spec ecosystem: system POR, guard-bands, manufacturing screen specs, and test insertion constraints. You need to know what drift looks like before it causes damage, and have the instincts to build checks that catch it early.

A proven track record of cross-org influence — methodologies others adopted, workflows you redefined rather than simply operated within. The ability to read silicon and productization outputs (speed, power, binning) and apply AI with genuine judgment: reviewable artifacts, and a clear view of where manual validation remains required.

Ways to stand out from the crowd: You've stood up a cross-org workflow from scratch and shipped automation that survived adoption across resistant partners, not as a proof of concept, but as infrastructure people actually depend on. You think like a workflow architect: optimizing stages, runtime, and toil across the system, not closing tickets on a single program and moving on.

The strongest candidates are the ones who ship the fix, then immediately identify the next class of problems, and start designing for it before anyone else has noticed it's coming. Every NVIDIA product depends on this. System intent and manufacturing reality have to stay aligned across every GPU, SoC, and CPU NVIDIA ships, across every generation and at every scale.

This role owns the workflow and applied-AI infrastructure that makes that alignment consistent and provable. It's foundational work with portfolio-wide impact, and it sits at the intersection of systems thinking, software engineering, and silicon expertise that very few people can operate across. If that's the kind of problem that gets you out of bed, let's talk.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until August 10, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.