Job description
In this position, you will work with the team that develops So. Cs. In this high-impact role, you will define and own the end-to-end signal and power integrity strategy for cutting-edge high speed Ser. Des. You will be responsible for ensuring robust interconnect performance from silicon to system. This position requires deep expertise in leading-edge Ser.
Des technologies (224G+), modern interconnect protocols, and system-level co-design.