雲端伺服器CPLD/FPGA/HW開發設計

1. Develop CPLD for Server application and basic power sequence control.
2. Proprietary design for system requirement through CPLD/ HDL development.
3. Develop FPGA for Server application.
4. Design and develop FPGA/CPLD digital logic using Verilog/SystemVerilog.
5. Implement FPGA/CPLD system-level simulation, functional simulation, and verification.
6. Work closely with EE engineers to integrate FPGA/CPLD into system architectures and troubleshoot issues.
7. Develop automation tools and build automated testing environment.

要求 / Requirements:

1. With bachelor’s degree of Electronics, EE, or CS.
2. With 3+ years HDL coding experience (Preferable to Verilog).
3. Possess basic knowledge of Digital Circuit Design ( Combinational Logic, Sequential Logic, FSM, etc).
4. Familiar with PC industry standards: SPI, I2C, USB, SGPIO, etc.
5. Familiar with UVM to verify FPGA/ ASIC.
6. Familiar with C, C++, or Python.
7. Familiar with board level design is a plus.
8. With good English competency in 4 skills, Toeic 600+.