Verification Engineer

Key Responsibilities

• Develop and maintain constrained-random UVM testbenches for RTL blocks and fullchip verification.
• Write functional coverage models and coverage closure plans to drive verification completeness.
• Author and execute directed and random test scenarios targeting corner cases and protocol compliance.
• Debug simulation failures, identify root causes in RTL, and collaborate with designers on fixes.
• Develop verification plans (VPlans) based on micro-architecture specifications and track sign-off metrics.
• Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting.
• Participate in design reviews, spec reviews, and silicon bringup activities. Required Qualifications
• B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on VLSI verification experience in an industry setting.
• Strong proficiency in SystemVerilog and UVM methodology (environments, agents, sequences, scoreboards). Strong proficiency in Specman language & methodology
• Experience with industry simulation tools: VCS, Xcelium, ModelSim/Questa.
• Solid understanding of digital design fundamentals, RTL coding, and microarchitecture concepts.
• Familiarity with assertion-based verification (SVA) and coverage-driven verification.
• Scripting skills in Python, Perl, or Tcl for automation and flow development.