Sr. Engineer, ASIC Design Verification

Sr. Engineer

• ASIC Design Verification Location: Bangalor (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, Media. Tek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Summary: This role is responsible for pre-Si verification and validation of complex So. Cs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team. The ideal candidate is a hands-on self-starter who can craft design specifications, verification suites and test-benches based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

Essential Functions

Develop verification methodology and testbenches for digital and mixed-signal blocks Test plan, coverage analysis and closure for parallel link and Ser. Des IP blocks and on-chip interconnects Design and contribute to design for test (DFT) methodologies Basic Qualifications: BS, MS in Electrical Engineering, Computer Engineering or equivalent 2+ years of ASIC verification experience 2+ years of System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification) 2+ years of scripting and/or programming skills Preferred Qualifications: Experience working on digital designs with multiple clock domains and clock dividers Post- place-and-route functional verification (NCSIM, VCS, Model.

Sim) Experience in verification of Ser. Des IP block interfaces in a complex SoC fabric environment Experience in verification of the PCS, PMA Ser. Des layers and internal Ser. Des digital backends Experience with verification of HBM memory interfaces (PHY and controller) Experience in formal model equivalence checking tools and verification methodology Programming experience in Python Recruiters: Principals only.

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