Lead Camera Electronics Engineer (Embedded Systems)

Galax. Eye aims to shape the future of Satellite Image Acquisition, providing the most meaningful datasets, thus helping businesses and governments make data-driven decisions based on insights from satellite imagery. We design and build advanced remote-sensing satellites and develop value-added services for geospatial analytics and infrastructure customers.

Role summary

Own the end-to-end architecture, design, bring-up, and qualification of the Camera Electronics (CE) stack for a multispectral payload: sensor/ROIC interfacing → high-speed capture → FPGA/SoC processing → DDR4 buffering → NVMe/SATA storage → downlink interfaces . You’ll lead a small CE team (HW, FPGA, firmware) and be the technical interface to Sensor and Systems and external vendors.

Responsibilities

Define robust CE architecture, ICDs, dataflow, clocks/resets, power domains, fault handling, safe-mode hooks. Trade studies for FPGA/SoC choice, storage, and high-speed links. Lead schematic + PCB design (high-speed + mixed-signal), DFM/DFT, EMI/EMC practices, grounding/fusing, thermal conduction design (space/vacuum context).

Interfaces: DDR3/DDR4 (SI closure), NVMe/SATA SSD (PCIe Gen4 x4+), Ser. Des transceivers (GTX/GTH/GTY/GTM), LVDS/CML. Own sensor/ROIC electrical interface spec, timing budgets, exposure/control loops, register maps. Hands-on with modern sensor links (e.g., SLVS-EC / sub-LVDS / LVDS ) and/or industrial vision links (Camera Link / CoaXPress / GigE Vision / USB3 Vision).

If ROIC is external/custom: drive requirements, review design/verification with ASIC partner, and own validation plan (bench → thermal → radiation strategy). (Modern ROICs often push very high-speed serial links—design must anticipate this.) Architect high-throughput RTL (DMA, DFX, buffering, packetization, compression hooks) and timing closure.

Boot chain (FSBL/U-Boot), QSPI/NAND, Linux/RTOS drivers, board support, and production-ready images. Hardware–firmware co-design: clean register maps, test hooks, driver APIs, HIL automation. SI validation (DDR + Ser. Des): eye diagrams, BER, link margining; lab instrumentation strategy. Test-as-you-fly mindset: unit tests, stress tests, long-duration soak, and environmental test support.

Lead a team of engineers to achieve the above milestones. Must-have (non-negotiable) > 6 years in embedded hardware + FPGA/SoC systems shipping real high-speed products. Deep hands-on with DDR3/DDR4 , PCIe (Gen3/Gen4) , high-speed transceivers, and board bring-up. Strong FPGA/SoC experience: Xilinx/AMD Zynq Ultra. Scale+ and/or Versal (preferred).

Fundamental knowledge of Real time operating system (RTOS) or Bare metal coding. Proven ownership: architecture → implementation → debug → validation → release. Comfortable leading a small team and driving cross-functional execution (systems, sensor, optics, software). Good-to-have (nice) Space-grade design practices: radiation mitigation (TID/SEE strategy), de-rating, watchdog/fault tolerance.

Familiarity with SLVS-EC or similar next-gen CMOS sensor interfaces (and related IP cores/ecosystem). DO-254 / aerospace process exposure; EMC pre-compliance and design-for-qualification. You’ll join a tight, multidisciplinary payload group that owns the MSI instrument end-to-end: mission-driven requirements, optical/opto-mechanical design, camera + control electronics, firmware/FPGA, and hands-on integration & testing.

We operate like a true startup engineering squad: direct communication, rapid problem-solving, and shared ownership. Decisions are made with a systems mindset, and plans turn into hardware quickly. Expect deep collaboration with data, business, and spacecraft teams as we mature the payload from prototype to flight-ready hardware.