ASIC / Physical Design Engineer

DiffLogic is on a mission to end matrix multiplication. We don't run models on chips. We build chips that are the model. That means tape-out isn't a milestone. It's the product. We iterate fast, we tape out frequently, and every spin ships smarter silicon than the last. We're hiring exceptional physical design flow engineers to take full ownership of the RTL-to-GDSII pipeline, including synthesis, P&R, power and timing analysis, signoff (DRC/LVS, etc.)

, foundry waiver negotiation, and handoff. You've taped out before, you close timing without being managed through it, and you're fluent in Synopsys and Cadence. You'll ship more silicon in two years than most engineers see in a decade. If you're obsessed with fully automatic flows and want to scale to >100mm² per month, we want to hear from you.