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Signal Integrity Engineer - DDR4/DDR5
$80k to $160k
Against the San Jose typical range
Job description
Johns Creek, GA or San Jose, CA About the Role We are a leading provider of chip and silicon IP solutions, seeking an exceptional Senior Engineer with signal integrity and package design expertise to join our Memory Interface engineering team. This full-time role involves developing products that boost data speed and security.
Reporting to the VP of Engineering, you'll focus on SI/PI modeling, analysis, and simulations for high-speed DDR applications up to 12800+ MT/s.
Key Responsibilities
Develop SI/PI methodologies; collaborate on studies and package designs for DDR products. Define specs and requirements (e.g., packaging, PCB routings, decoupling, simulations, jitter analysis) with design/validation teams. Guide design team via SI/PI studies, simulations, and correlations for top SI performance (e.g., optimal RMT scores).
Partner with customers on optimal SI/PI solutions. Support debug and lab bring-up.
Requirements
Qualifications
MS/PhD in Electrical Engineering; 10+ years experience, including DDR4/DDR5 focus. Experience simulating high-speed memory (DDR4/DDR5) and/or SERDES. Strong in EM and transmission line theory. Expertise in equalization (FIR/FFE/DFE/CTLE). Proficient in package/PCB design: editing APD/Allegro files, SI/PI-driven BGA, system simulations.
Hands-on correlation of simulations with lab measurements (scopes, TDRs, VNAs). Desirable: Server system knowledge (CPUs to DRAMs); crosstalk/jitter in source-synchronous interfaces for low BER. Skilled in Spice, ADS, HFSS, Q3D/PowerSI. Plus: RedHawk/Totem, XcitePI, Virtuoso familiarity. Valued: Lab experience with passive components, margins, noise (scopes, VNA/TDR).
Preferred: Basic high-speed link circuit knowledge. Excellent communication, writing, presentation skills for customers/teams. Innovative, self-motivated team player with leadership.
Benefits
3 days/week in office Compensation: Johns Creek, GA: Base midpoint ~$180K; Bonus 20%; RSUs $80K–$160K. San Jose, CA: Base midpoint ~$210K; Bonus 20%; RSUs $92K–$184K. If you're a technical expert in SI/PI, EM simulation, transmission lines, and lab tools like ADS/HFSS/PowerSI, apply now. Push high-speed memory boundaries with us!
Description copied from Talentry's careers page. Read the full posting before you apply.
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