Design Verification Engineer | Sensing

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this position, you will be working on advanced mixed-signal sensor circuits using state-of-the art process technology, as well as be involved in the digital and AMS verification of high-performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.

In this role, your responsibilities will include the following. Develop detailed Verification/Test plans using specifications to cover all the digital/analog functionality/features of a mixed-signal chip for our next generation designs. Develop SystemVerilog chip-level testcases based on the verification plan. Simulation, Testcase debug and Verification closure for the digital/analog functionality of Mixed-signal chips, at chip-level in digital and AMS environment.

Finding design bugs with break-the-design mindset and ensuring design is bug-free and robust. Develop SystemVerilog based behavioral models for the analog blocks and integrate them in the chip-level verification environment. Running regressions and DV closure activities. Work closely with design and systems teams to review/close spec gaps and design bugs, as they arise.

Design for testability using ad-hoc, Full scan, IDDQ, VBOX, ATPG, BIST Drive documentation, reviews and verification flow improvement strategies. Be proactive in risk assessment and drive solutions to mitigate them. Minimum requirements: Masters degree in Electrical Engineering or related field. 3+ years of related experience.

Strong hands on working experience in Digital/AMS verification for Mixed-signal chips. Strong programming skills using SystemVerilog in verification. Robust in verification approach and strong in fundamentals of DV flows and concepts. SystemVerilog and class-based verification knowledge.

Preferred qualifications

Experience in writing an exhaustive verification plan from the specs. Experience in chip-level testcases in SystemVerilog. Experience in metric-based Verification closure using Code and Functional coverage. Experience in random/constrained random verification. Experience with Cadence simulation and debug tools. Experience with UART, SPI, I2C communication protocols.

Good in debugging skills. Ability to work independently and self-driven/motivated person.