Principal SoC Signoff Engineer

Principal Engineer, SOC signoff About Global. Foundries Global. Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global.

Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: The Principal Engineer, SoC Signoff has a deep understanding about how timing constraints are to be written across functional and test modes.

They not only leads but mentors engineers towards designing and delivering full chip, complex Ips, and critical interface multi-mode timing constraints. This role drives the creation of constraints for custom integrated circuits (ICs) from specifications, co-ordinate across stake holding teams not only to create constraints and validate them, but also define margin methodologies and develop process for every SoC design we develop at MIPS.

Your Job As a lead constraint developer, you will own and drive all phases of constraint development not only for complex So. Cs but also complex Digital, AMS, and SERDES IPs You will define margins for ASIC implementation, STA sign-off – from spec to production You will establish process to support MV/DVFS STA signoff and device shift left methodologies for STA You will technically mentor a high‑performing team/New college graduates You will also champion the development, deploy and maintain STA methodologies using AIML with leading EDA undefined Other Responsibilities Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field. 12+ years of industry experience, at least 2+ in subsystem RTL design, 6+ years in writing STA constraints, 4+ years in STA signoff Deep hands‑on expertise in Constraint development – functional and test modes for full chip, sub-chip digital, analog, mixed signal designs and source-synchronous designs/interfaces Expert in writing constraints for MV/DVFS, advanced in UPF & expert in SDC Expert in STA sign-off margining & has setup process to establish grounds-up Deep hands-on expertise in STA signoff execution – mode reduction, methodology infrastructure Has carried out timing signoff reviews for So.

Cs in production. Strong proficiency with Synopsys, Cadence, or Siemens/Mentor EDA tools. Excellent leadership and communication skills. Strong analytical mindset Preferred Qualifications Proven track record of delivering custom silicon across diverse application domains. Inspirational leadership style with a passion for mentoring and scaling high‑performance teams.

Customer‑centric, proactive problem solver.Passion for continuous learning and driving adoption of industry best practices. Synopsys EDA tool set expertise. Agentic AI exposure Global. Foundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.All offers of employment with Global. Foundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia