SoC Implementation & Tapeout Engineer

Job Description: SoC Implementation & Tapeout Engineer Company: Ananant Systems Location: Noida / Bengaluru Department: Silicon Engineering — SoC Implementation Experience: 5–15 years Education: B.Tech / M.Tech / PhD — Electronics, Computer Engineering, or Electrical Engineering About the Role Ananant Systems is developing a proprietary AI-native DSP SoC targeting 5G/6G wireless, Edge AI inference, Vision AI, camera, video, and radar applications.

We are looking for an experienced SoC Implementation & Tapeout Engineer to own end-to-end SoC integration, synthesis, timing & power sign-off, DFT, and tapeout execution — from RTL handoff to GDSII delivery and post-silicon support. The role reports directly to the Chief Architect / CTO.

Key Responsibilities

Integrate DSP datapath IPs, processor subsystems, memory controllers, and high-speed peripherals (PCIe Gen3/4, USB3, JESD204B, MIPI CSI-2/DSI, DDR/LPDDR, etc.) into the top-level SoC. Define and implement clock, reset, and power architectures (UPF) across multiple voltage domains. Drive hierarchical synthesis, STA timing closure (Prime.

Time), lint/CDC checks, and formal equivalence across all design stages. Perform dynamic & static power analysis and optimization to meet power budgets. Own DFT implementation: scan chain stitching, MBIST/LBIST, JTAG TAP, and boundary scan. Manage complete tapeout flow — sign-off checklist, ECOs, documentation, and foundry handoff.

Support post-silicon bring-up, scan test debug, and silicon characterization.

Requirements

Synthesis (DC/Genus), STA (Prime. Time), Lint & CDC (Spyglass), Power (UPF/Joules), Tapeout execution & sign-off. Advanced level: DFT architecture, Formal Equivalence (Formality/Conformal), Clock/Reset design, Peripheral IP integration (PCIe, JESD204B, MIPI, DDR). Strong understanding of FinFET nodes and multi-domain SoC integration.

Mandatory Experience Named contributor on at least 2 commercial tapeouts at 22nm or below. Direct ownership of sign-off (synthesis/timing/power/DFT) for at least one IP block or SoC subsystem through GDS handoff. Experience in post-silicon debug or bring-up support. Strong Advantage Tapeout experience on heterogeneous So.

Cs with DSP + AI + Multimedia accelerators. Hands-on work with high-speed Ser. Des (PCIe, JESD204B) and DDR/LPDDR controllers. Prior FinFET tapeouts (16nm/12nm/7nm).

Benefits

What We Offer Full ownership of implementation and tapeout of a next-generation AI-native DSP SoC. Direct collaboration with a Chief Architect having 20+ years of 4G/5G modem silicon experience. Access to advanced FinFET technology through foundry partnerships. Competitive CTC + meaningful ESOPs in an early-stage semiconductor startup.

To Apply: Send your CV, a list of tapeouts you have contributed to (with your specific sign-off responsibilities), and any publications/patents to: deepikka.dubey@ananantsys.com