Senior Staff Engineer

Position Summary

About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile So.

Cs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas.

Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Position: Design Verification Engineer Roles and Responsibilities Independent Verification Ownership of IP DV.

Collaborating with various cross functional teams at multiple geo locations as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts) Domain: AXI, PCIe, UCIe protocol experience is highly preferred Skills: Must have experience in developing test benches for IP/Subsystems/SoC.

In depth knowledge and hands on experience in the execution of verification of SoC/Sub System/IP DV. Previous experience of independently driving IP DV projects from ability to lead a team by providing technical guidance, as well as be part of execution by debugging and SoC architecture understanding capabilities. Strong hands on experience with common verification tools and methodology including UVM/ System Verilog/CDV/MDV, DV signoffs.

Must have a strong domain expertise in one or more following areas

• AXI/PCIe/UCIe. Experience in Hybrid testbenches (SV, SystemC, Python) and SystemC based reference model test vectors/stimulus based verification is desirable. Experience – 7 to 10 Years of experience Qualifications B.Tech/B.E/M.Tech/M.E Skills and Qualifications Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India
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