Principal HS Digital Design Engineer

Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products Define digital subsystem architectures Lead RTL development and integration Drive design reviews and quality standards Support verification and implementation teams Mentor design engineers Who we are looking for MSc or PhD in Electrical Engineering 10+ years digital IC design experience RTL design (Verilog/System.

Verilog) High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage Interface protocols and clock-domain crossing Synthesis and timing analysis Advanced CMOS node experience, including FinFET and/or FD-SOI, is required Please contact Hana Krsul for further information via Hana.

[email protected] or +43 664 9665611 .