UFS Design Verification Engineer

We are looking for an enthusiastic UFS Design Verification Engineer with 7–8 years of proven professional experience to join our IP Design team. As a UFS Design Verification Engineer, you will be part of a highly competent team verifying UFS IP and ASIC implementations through a disciplined, coverage-driven verification process.

You will apply strong protocol knowledge and hands-on UVM expertise to deliver robust, high-quality verification collateral. Your Main Responsibilities Develop and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases. Verify UFS functionality, protocol behavior, and relevant corner cases across supported configurations.

Execute and validate regressions, investigate failures, and partner with design and integration teams to drive resolution. Implement and track code and functional coverage, driving closure against defined verification objectives. Maintain clear verification documentation, including test plans, results, and issue tracking.

Requirements

7–8 years of relevant ASIC/IP design verification experience. Strong understanding of ASIC design verification methodologies and principles. Proficiency in SystemVerilog and UVM. Strong UFS protocol knowledge. Demonstrated experience in testbench and testcase development, regression execution and validation, and code and functional coverage.

Preferred: proficiency in Perl and/or Python scripting. Preferred: experience working with foundry data from TSMC, Intel, and/or Samsung.