UAL Design Verification Engineer

We are looking for an enthusiastic UAL Design Verification Engineer with 4–5 years of proven professional experience to join our IP Design team. As a UAL Design Verification Engineer, you will be part of a highly competent team working on complex IP and ASIC designs. You will contribute throughout the verification lifecycle—from testbench architecture and test development to regression analysis, coverage closure, and sign-off readiness.

Your Main Responsibilities Develop and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases. Verify UAL functionality and interfaces, with particular focus on Ethernet integration and basic PCIe protocol interactions. Execute regressions, analyze failures, and collaborate with design and integration teams to resolve issues.

Develop and track code and functional coverage, driving coverage closure against the verification plan. Document verification results, issues, and readiness for project milestones.

Requirements

4–5 years of relevant ASIC/IP design verification experience. Strong understanding of ASIC design verification methodologies and principles. Proficiency in SystemVerilog and UVM. Strong UAL and Ethernet knowledge, together with basic PCIe protocol knowledge. Demonstrated experience in testbench and testcase development, regression execution and validation, and code and functional coverage.

Preferred: proficiency in Perl and/or Python scripting. Preferred: experience working with foundry data from TSMC, Intel, and/or Samsung.