24 open roles
Senior PCB/FPGA Engineer
$150k to $250k
Against the Palo Alto typical range
Job description
CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. **Lasers will fail. Compute shouldn’t.**The ambition is simple:Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.
We are hiring a Senior PCB/FPGA Engineer to own the electrical hardware that drives and reads out our photonic integrated circuits. You will design custom high-speed and RF boards, build FPGA-based control and test systems, and bring up optical transceiver hardware running at high baud rates.
This is a hands-on role at the boundary of photonics and electronics. You will work daily with photonics, test, and firmware engineers, taking boards from schematic to validated lab hardware.
What you'll do
- Own custom PCB designs end to end: architecture, schematic capture, stackup selection, layout or layout review, fab/assembly hand-off, and bring-up.
- Design high-speed and RF boards for optical transceivers, including driver, TIA, and modulator/photodetector interfaces.
- Engineer controlled-impedance channels from DC to 50+ GHz: transmission lines, transitions, vias, launches, connectors, and RF probe/wirebond interfaces to PICs.
- Run signal and power integrity analysis (insertion/return loss, crosstalk, PDN impedance) and correlate simulation measurements.
- Develop FPGA designs for transceiver test and control: high-speed data links, PRBS generation and BER testing, DAC/ADC interfaces, and closed-loop control of bias, heaters, and TECs.
- Bring up and debug boards in the lab using high-speed oscilloscopes, DCAs, BERTs, VNAs, and optical test equipment; drive root-cause analysis on SI, thermal, and layout issues.
- Partner with photonics engineers on electro-optic co-design (packaging, RF launch to the PIC, thermal management) and with firmware/software teams on control interfaces.
- Manage PCB vendors and assemblers, write design documentation, and lead design reviews.
Required qualifications
- BS/MS in Electrical Engineering or a related field, with 7+ years of hands-on hardware design experience (3S+ with a PhD).
- Direct experience designing or bringing up optical transceiver hardware at high baud rates (≥ 50 GBd), such as 400G/800G/1.6T modules, line cards, or evaluation boards.
- Proven RF PCB design experience: controlled-impedance and coplanar waveguide structures, low-loss laminates and transitions validated to 40+ GHz.
- Multiple custom PCBs taken from concept to working hardware, including high-layer-count, mixed-signal boards with sensitive analog and high-speed digital sections.
- Production-quality FPGA development in Verilog/SystemVerilog or VHDL on AMD/Xilinx or Intel/Altera devices, including high-speed transceivers, timing closure, and hardware debug.
- Strong lab skills with high-bandwidth oscilloscopes, VNAs, BERTs, and TDR, and comfort correlating measurements to simulation.
- Clear written and verbal communication, and the ability to own work across disciplines with little supervision.
Compensation
includes a base salary of $150,000–$250,000 and equity in CScale. Final offers depend on experience, market conditions and location.
Description copied from Cspeed IO's careers page. Read the full posting before you apply.
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