Packaging Engineer (Module Package Development)

Company Overview Our client is a Global Semiconductor Pioneer & World Leader in High-Performance Analog, Mixed-Signal & Integrated Power Processing Technologies. Operating an advanced back-end R&D and manufacturing hub in Melaka, the company designs and manufactures cutting-edge integrated circuits and module solutions powering data centers, AI accelerators, cloud computing servers, and automotive architectures.

To support next-generation power density requirements and high-performance computing platforms, the Package Development team is seeking a Senior/Lead Packaging Engineer.

Position Overview

Reporting to the Packaging Section Manager, the Packaging Engineer (Module Package Development) leads the end-to-end package development architecture for Substrate-Based Power Modules and Multi-Chip Modules (MCM). Focusing on advanced packaging solutions for AI accelerators, high-density computing chips, and server hardware, this technical role drives multi-layer substrate layouts, thermo-mechanical characterization, material qualification, and NPI transfer into mass manufacturing at the Melaka plant.

Key Responsibilities

1. Module Package Architecture & Design Development Lead package engineering development for Substrate-Based Power Modules, Flip-Chip, Multi-Chip Modules (MCM), and System-in-Package (SiP) architectures targeting AI acceleration and data center applications. Perform packaging design evaluations, multi-layer substrate routing layouts, parasitics assessment, and thermal management optimizations. Qualify advanced packaging materials—including organic/ceramic substrates, Epoxy Molding Compounds (EMC), clip-bond materials, and high-conductivity die-attach adhesives.
2. Reliability Characterization & Material Validation Evaluate thermo-mechanical strain, warpage, parasitic inductance, and Board-Level Reliability (BLR) under Thermal Cycling (TMCL) and Moisture Sensitivity Level (MSL) stress conditions. Manage NPI qualification vehicles from initial concept, prototype build, and reliability testing stages through to High-Volume Manufacturing (HVM) readiness.
3. Cross-Functional & Supplier Collaboration Collaborate with global silicon design teams, substrate vendors, leadframe suppliers, and internal assembly process engineering teams to resolve complex mechanical and thermal packaging constraints. Establish design rules, substrate design guidelines, and package outline drawings for new product platforms.

Requirements

Bachelor’s or Master’s Degree in Materials Science, Mechanical Engineering, Electrical/Electronic Engineering, Microelectronics, or a related discipline. Work Experience: 5 to 10 years of dedicated experience in semiconductor package development or advanced packaging assembly. Domain Expertise: Specific expertise in Substrate-Based Power Modules, MCM, Flip-Chip, or System-in-Package (SiP) package architectures.

Technical Skills: Deep understanding of thermo-mechanical stress modeling, substrate design rules, material characterization, and reliability standards (JEDEC, BLR, MSL).